Assignment No. 04
Semester: Spring 2013
CS501: Advanced Computer Architecture
Total Marks: 20
Due Date: 19-06-13
Instructions
Please read the following instructions carefully before assignment submission.
It should be clear that your assignment will not get any credit if:
The assignment is submitted after the due date.
The submitted assignment does not open or file is corrupt.
The assignment is found to be copied from the internet.
The assignment is found to be copied from other student.
The assignment submitted is not according to required file format (.doc).
Objective
The objective of this assignment is:
To assess your overall understanding of Computer Architecture and Organization
To assess your overall understanding of Computer Instructions
To assess your overall understanding of Fetch, Decode and Execute Cycle clock in pipeline structure.
Note:
• The assignment should be in .doc format.
• Assignment .04 covers lecture 17-24. You can also consult reference books for help.
• Students are advised to submit their assignment as early as possible in order to avoid any sort of inconvenience like Load shedding etc.
Question: Marks 20
Keeping in view the stages of pipelining, explain X3, Y3, Z4 and Z5 registers.
Addresses Instructions
100 sub r1, r2, r3
104 ld r5, [5(r7)
108 br r6
112 str r4, 56
…
200
Further you are required to explain how the given SRC (Simple RISC computers) code will be executed through the five stages of a pipelined processor.
Marking scheme (Total marks 20)
5 marks (X3, Y3, Z4 and Z5)
3 marks for each step (3*5 = 15)
NOTE:
Provide one line explanations for X3, Y3, Z4 and Z5 while explain clock cycle steps within 3-4 lines, otherwise answer will not be accepted and marked zero.
GOOD LUCK
No comments:
Post a Comment