Assignment No. 02 Semester: FALL 2010 Advance Computer Architectuer-CS501

	Assignment No. 02 Semester: FALL 2010 Advance Computer Architectuer-CS501		Total Marks: 20 Due Date: 25-11-2010
Objective: To learn and understand basic concepts of Logic Design and Control Signals Generation in SRC. Instructions: Please read the following instructions carefully before solving & submitting assignment: Assignment should be in your own wordings not copied from net, handouts or books. It should be clear that your assignment will not get any credit (zero marks) if: o        The assignment is submitted after due date. o        The submitted assignment does not open or file corrupt. o        The assignment is copied (from other student or copy from handouts or internet). o        Student ID is not mentioned in the assignment File or name of file is other than student ID. For any query about the assignment, contact at cs501@vu.edu.pk GOOD LUCK
What will be the logic levels on the external SRC buses when each of the given SRC instruction is executing on the processor? Complete Table: A all numbers are in the decimal number system, unless noted otherwise. (Assume the required missing information if necessary).  Also Specify memory addressing modes for each of the SRC instructions given in Table. SRC instruction RTL Equivalent Address Bus<31….0> Data Bus <31….0> MRead MWrite Addressing mode Ld r9,4(r2) Ld r4,4 Ld r3, M[r3] Move r3,  r2 Table: A Assumptions: All memory content is aligned properly. In other words, all the memory accesses start at addresses divisible by 4.  Value in the PC = 000DC348h Memory map with assumed values Register map with assumed values  Download from vulms for clear vision.